HohenlindnerStrasse 18

85622 Feldkirchen


Tel +49 (0)89 24223788



Alessandro Ogheri

Personal information

I was born in Italy, in Verona the 5th of October 1973. I’m married with Giorgia.  

We have a daughter, Lisa, and a son, Thomas.


April  2014 – current freelance                        Infineon,Munich

Freelance consulting engineer for Infineon Semiconductors AG

I am working on Firmware in assembly for the flash memory controller family of devices, and also on the testbenches to verify it using the simulation tools that permits to simulate the VHDL model of the controller in which the uController is instantiated.

April  2012 – March 2014 freelance                        Intel,Munich

Freelance consulting engineer for Intel Mobile Communications

I worked on SystemC based TLM-abstraction-level Reference Models and the environment around them.

January  2010 – April 2012 freelance                        Infineon,Munich

Freelance consulting engineer for Infineon Semiconductors AG

I worked on Specman- eRM- based environments for the verification of some ASICs used in the not volatile memories application area.

April 2009 – October 2009 freelance                           NEC,Düsseldorf

Freelance consulting engineer for NEC Electronics

I developed SystemVerilog- OVM- based environments for the verification of some ASICs used in the automotive application area.

April 2008 – October 2008 freelance                                    Kista,Sweden

Freelance consulting engineer for Ericsson

I developed specman-based environments for the verification of some ASICs used in base radio stations.

January 2008 – March 2008 freelance                                           Munich

Freelance consulting engineer for Micronas GmbH

I developed further some specman- and systemc- based verification environments.

October 2007 – December 2007 freelance                 E.S.A., Netherlands

Freelance external product assurance manager for E.S.A.

Between  October 2007 and December 2007 I have been responsible as external product assurance manager for a project with E.S.A. (European Space Agency) in Holland. I made the work partially remote from Italy, from Germany and partially on site in Holland. My duties have been the development of the product assurance plan, where the action items that must be delivered to ensure the required quality assurance levels of the device are listed. Furthermore, I had to develop the test plan for the verification activities of the device (which is a vibration and shock test platform for satellites, called HYDRA)

August 2007 – September 2007 freelance                          Kista, Sweden

Freelance consulting engineer for Infineon  AG

In August 2007 and September 2007 I have been doing consulting for the Kista, Sweden office of Infineon Semiconductors AG. I developed a Specman verification environment for a dual-bus multi-master and multi-slave system. The environment is built in compliance with the Specman eRM methodology and uses some eVCs (e Verification Components) which are provided with the Specman tool or bought separately: the vr_ahb AHB verification component and the vr_ad memory and registers modeling package.

November 2006 – July 2007 freelance                                           Munich

Freelance consulting engineer for Micronas GmbH

On the 1st of November 2006, I started my own business. In between, I’ve got the opportunity to develop pretty advanced verification environments based also on the methodics of Assertion Based Verification and Coverage Driven Verification using the Specman Tool and its “e” language of Verisity Inc.

April 2005-November 2006     Micronas,GmbH                             Munich

Verification Project leader

In April 2005, I moved to Micronas GmbH, a swiss semiconductor company which has an office in Munich too. I take the verification project leader responsibility for the cpu(s)-enclosing block of the newly developed graphical chip.

My duties comprise,but are also not limited to:

the development of the verification plan

the introduction of efficient verification methodics and techniques and

the management of the activities and the tracking of their effectiveness.


2001–March 2005          Cadence Design Systems,GmbH            Munich

Senior Support Engineer

In 2001, on request from the company, I moved to the post-sales support department.

There, I’ve been involved mainly supporting our products in the front-end digital simulation and logical verification area (i.e. supporting our vhdl, verilog, SystemC simulators, our code-coverage tools, our formal equivalence checking tools and our transaction-based and assertion-based digital simulation tools).

Inbetween, I remained anyway in contact with my old department, that sometime requested my help working part-time as consulting engineer at customer sites.

Another duty associated with the support job in Cadence is to deliver courses. I’m teacher for the VHDL Verilog, SystemC, C++ (Feabhas associated certified trainer) languages trainings, and for the ncsim simulators trainings.

In this department I had also the opportunity to work (sporadic) in the synthesis and static timing analysis area, using mainly our BuildGates and PKS products (in Infineon as consulting engineer I had the opportunity to work with Synopsys Design Compiler).

I have developed a Java-Servlets and JSP-Based training for the SystemC course of Cadence, making it more suitable for a delivery which is media independent (web-server, cdrom) and platform independent (running on the JVM of the hosting web-server).


2000–2001                    Cadence Design Systems,GmbH            Munich

Design consulting engineer

I worked for approx 1 Year and an Half as design consulting engineer in the front-end area. My duties have been:

·         Coding of vhdl- or verilog- based rtl synthesizable descriptions of devices (specially, looked at parts of the irq controller for the sle88c and sle66c of Infineon Semiconductors A.G. for debugging) and behavioral testbenches.

·         Development of the associated test development and test-running environment based on Perl-Scripts.

·         Development of tests to run in the regression suite of the mentioned devices and for the Tricore architecture of Infineon, written in the assembly programming language of the devices and run on the simulated chip.


1999–2000                    EnAip Veneto                                Verona, Italy


I worked as teacher for one course on electronic and one more specific on microcontrollers based embedded design using the Motorola hc11 as case study.


1998–2000                    I.Pro.M. s.r.l.                                  Verona, Italy

Embedded systems designer

I worked as developer of devices for digital communication networks on railways based on the IEC standards for these kind of applications. My duties have been to develop the printed circuit boards using Orcad and to route them using Veribest, to develop the programmable logic devices used on them (Xilinx 9500 and SpartanII series and QuickLogic pasic fpgas), to develop the software for the commercial microprocessors used on the boards (Assembly and C for the MC68302 / MC68360 /Quadd series, Microchip PIC17cxxx series, Siemens C166 and Motorola HC11). Web sites of the company: http://www.farsystems.it where some of my boards are visible: MSC450, MSC442, MSC441.


1992–1998                    Universita’ degli Studi di Padova    Padova,Italy

Graduated in electrical engineering  with a thesis titled “development of an ASIC prototype for the management of a digital communication network on railways using QuickLogic FPGAs” (job carried on in I.Pro.M. s.r.l.)


Running, guitar playing.


Italian (mother tongue), English (discrete), German (good)

Detailed skills

C/C++ programming language (Feabhas associated trainer inside of Cadence Design Systems) with knowledge of the Visual C++ 6.0 environment and of the Renesas HEW environment, assembly for the Motorola MC68302 / MC68360 32-bit families and MC68HC11 8-bit family, for the Microchip PIC series and for the Infineon Tricore architecture.

Java and JSP/Servlet technology knowledge (usage of Borland Jbuilder and Sun’s Netbeans).

Worked with the RedHat Linux operating system, Solaris, HP-UX, AIX and Win2000 operating system (all families for which Cadence sells EDA-tools).

Ncsim and Modelsim Verilog/VHDL HDL simulators knowledge.

Ambit buildgates synthesis tool and Xilinx WebPack ISE synthesis tool knowledge.