First post

Please use this category for methodic-related questions and suggestions.

2 Responses to “First post”

  1. alex says:

    Hi dear all, my next activities will be with Micronas Semiconductors GmbH in Munich, where I will be an employee until October, the 31st.
    What will follow will be the extension and the completion of our verification environment for a block of the next design.

    I post here in the methodic section some information and some comments about what we delivered and enjoyed to realize so far!

    The verification environment consists of three main components:

    on one side, we have a verilog behavioral testbench which takes care mostly only of the “trivial wiring” and which instantiates:

    –> the verilog RTL design
    –> the SystemC reference model (which is partially cycle accurate/ partially (in some blocks) transaction level modeled)

    On top of that, we have a Specman environment which drives the inputs to the verilog testbench and collects the results from the two outputs (the one coming from the RTL design and the one coming from the SystemC reference model).
    The specman environment performs checks and scoreboarding, and random based constrained generation of the stimuli (obviously, perhaps, being these the most compelling reasons to use an HVL environment from the beginning!)
    To stimulate the design, we use specman sequences and we instantiate eVCs (e Verification Components) that we bought, and configured to suit them to our needs (let suffice to say that we have 41 different input ports in our design each one with a different OCP2.1 profile)

    This work is a really exciting one, giving me (and a colleague, the author of the Verilog design) a very interesting opportunity to mix SystemC coding, seeing the real benefits of having a reference model at disposal for verification purposes, but also for rethinking of some concepts that the “concept engineering” department conceived at the beginning of the conceptualization phase, and random-based stimuli generation to stress both the design and the model under all corner cases.

    Kind Regards,

  2. alex says:

    Thank you!

    BtW it seems that also the next contract will be a verification-related one: from the first days of August I will be working with a company for the development of a Specman- based verification environment (working from Munich, Verona (my city in Italy!) and Stockholm)…


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