I'm a 47 years old Electrical Engineer providing trainings and consulting in the area of HDL Description
Languages (VHDL and Verilog), SystemC, C++, SystemVerilog and Specman- e
On this Web Page you will be able to have a look at some excerpts from the training slides, so that you can
evaluate the offering before committing to a course.
we are Cadence Verification Alliance partners and Mentor Questa Vanguard partners now!!!
three new employees, Matteo De Luigi , Pierluigi Picciau and Max Giacometti, are working for us now (see the site blog)
we are Synopsys VMM Catalyst partners now!